The TL494 is a PWM chip made by Texas Instruments. It's datasheets can be found here:
An important part of the design process is the ability to simulate circuits. LTSpice is an excellent SPICE simulator program provided by Linear Technology Corporation.
It can be downloaded here:
Unfortunately, an offical LTSpice model for the TL494 chip does NOT exist, to my knowledge. I was able to find an unofficial LTSpice model that works fairly well here:
Place the TL494.asy file into /LTSpiceIV/lib/sym/Misc and the TL494.sub file into /LTSpiceIV/lib/sub/eigene
The second directory needs to be this way or it will not work.
In the next section we will simulate with this model, discover its limitations, as well as techniques for overcoming these limitations.
Test Jig Simulation Circuit
There is a test jig available from where I found the unoffical LTSpice model, but I found it didn't simulate properly "out of the box". The following test jig that I made should simulate with no issues. Notice that the voltage source supplying Vcc is ramped up, rather than being a DC source. This allows the simulation engine to simulate the circuit with no errors. The error amplifiers (EA's) are wired into max PWM configurations at the inputs, with a SIN wave source manipulating the feedback (FB) pin. The sine wave swings from a 2V offset between 3.5V and 0.5V, providing a minimum to maximum excursion of PWM duty cycle.
Test Jig Simulation Run
After running the simulation of the test jig circuit, you get the following output. I placed voltage and current markers at nodes of significance, such as the PWM output and sense resistor current, etc.
TL494 LTSpice Model Text and Issues Discussion
When I first used the TL494 LTSpice model, I noticed that the voltage at the PWM outputs went only up to 4.8V, despite having 13V at the VCC pin. This did not make sense, since the saturation voltage of the internal transistors was only 2.5V maximum according to the datasheet. So I would expect a 10.5V minimum PWM output voltage. 4.8V at the PWM pins is ok to drive logic level MOSFETs, but standard MOSFETs will NOT fully enhance at such a low gate voltage. The model therefore had to be tweaked. I list the original model text below:
Notice that the bases of the BJT output transistors, Q1 and Q2, connect to nodes N003 and N013, respectively. These nodes in turn connect to nodes N002 and N012 through 470 ohm resistors R1 and R2. R1 and R2, in turn, are connected to logic functions A2 and A3, whose high output voltage is 4.8V (the vhigh parameter setting). That was the reason for the 4.8V voltage at the PWM output pin. Note, that this is the case for a voltage follower configuration of the PWM output pins connection. My solution for this was the following:
At first I tried to simply increase the vhigh parameters of A2 and A3 from 4.8V to 13V, but this did NOT work. It is not clear why. I then opted for inserting 100 ohm resistors, and E elements between the bases of the output transistors Q1 and Q2. The E elements have a gain of 2.1875V/V. This will provide 4.8V X 2.1875V/V = 10.5V at the output of the PWM pin. The 100 ohm resistors were required by the simulation engine to isolate the logic elements A2 and A3 from the E elements E1000 and E1001. This gain can be manually adjusted to the needs of the user. Note that this voltage is fixed, and will not simulate the current dependent satuarion voltage of the output transistors detracting from the supply voltage. This is a limitation of this model.
The fixed LTSpice model is provided below: